Flash memory has the advantages of data retention, high reliability, suitable for large amount of data read and write; hence, flash memory is widely used as data storage, such as, video or audio data. Currently, flash memory is applied to a wide range of consumer electronic products, such as, thumb memory stick, digital camera, digital video camera, mobile phone, and so on.
For the convenience of description, the following uses the Intel NAND flash memory as example. Refer to Intel NAND Flash memory Specification for details.
FIG. 1 shows a schematic view of a conventional system for controlling flash memory. As shown in FIG. 1, a conventional flash memory control system includes a flash memory controller 10 and flash memory 20. The control interface includes a ready/busy (RB) signal, a chip enable (CE) signal, an address latch enable (ALE) signal, a command latch enable (CLE) signal, a read enable (REN) signal, a write enable (WEN) signal, a write protect (WPN) and an input/output (IO) bus.
FIG. 2 shows a flowchart of a conventional page read operation. As shown in FIG. 2, the operation of page read by flash memory controller 10 on flash memory 20 starts with step S10. In step S10, flash memory controller 10 uses the control interface to transmit the page read command, including command code 00h and 20h on IO. Step S20 is to wait for RB to rise, because flash memory 20 is not ready for page read operation when RB is dragged to low level by flash memory 20. Therefore, IO does not have the page read data. Once flash memory 20 releases RB, RB will be raised by an external resistor to high level. Step S30 is to execute page read operation to read the data of the entire page. In step S30, REN is dragged to low level and the correct data is captured on
IO. REN can be repeatedly raised up and dragged down to read the data of the entire page, as shown in FIG. 3, which illustrates a waveform of a conventional page read operation.
However, the rising time for RB is very long, usually requiring the time for the flash memory to be lowered to a low level (typically of 25 μs-50 μs, depending on the flash memory) plus the time for the external pull-up resistor to pull up to the high level after flash memory is released (usually 3 μs, depending on the pull-up resistor). Furthermore, for high capacity flash memory comprising a plurality of physical flash memories, a plurality of RB signals are required, leading to the increase of the number of pins and affecting the circuit layout. Therefore, the flash memory manufacturers usually suggest the use of state bits in the internal register to determine whether the flash memory is ready for page read, instead of the RB signal mechanism.
FIG. 4 shows a schematic view of another waveform of a page read operation. As shown in FIG. 4, without referring to RB signal, the state bit of the state register is read to determine whether the page read can be performed. If the read state is at high level, the page read can be performed; otherwise, if at low level, the state bit must be continuously read and tested. However, when the state bit is at high level, and REN signal is lowered to low level to capture the memory data on IO, IO cannot display the correct memory data; instead, the previous contents of state register are displayed. Therefore, the conventional page read technique cannot perform without the RB signal.
It is therefore imperative to devise a method for controlling flash memory so that the page read can be read without the RB signal to solve the aforementioned problems.